1. Field of the Invention
The present invention relates to memory devices based on chalcogenide materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
Research has progressed to provide memory devices that operate with low reset current by adjusting a doping concentration in phase change material, and by providing structures with very small dimensions. One problem with very small dimension phase change devices involves endurance. Specifically, the resistance of memory cells made using phase change materials in a set state can drift as the composition of the phase change material slowly changes with time over the life of the device. Co-pending U.S. patent application entitled DIELECTRIC MESH ISOLATED PHASE CHANGE STRUCTURE FOR PHASE CHANGE MEMORY, application Ser. No. 12/286,874, filed 2 Oct. 2008, addresses some of the issues discussed above related to changes in composition of the phase change memory during the first few cycles operation. Application Ser. No. 12/286,874 is incorporated by reference as if fully set forth herein.
This drift can cause problems with reliability and increase in complexity of control circuitry needed to operate the devices. For example, if the resistance drifts on SET or/and RESET state cells, phase change speed changes, the dynamic resistance of the cells may change, different retention behaviors (resistance stability) are encountered, and so on. One result of these problems is that the sensing circuitry required on the devices must handle wider ranges of resistance for each of the memory states, which typically results in lower speed operation. Also, the set and reset processes must account for varying bulk conditions of the memory cells even within a single memory state, which typically results uneven set and reset speeds across the array.
Accordingly, it is desirable to provide a memory cell structure having more stable operation over the life of the device.